• [00:10:20] <nextime> hello. TI will close omap departement. So, what happen to beagleboard in future? will they change cpu using another arm cpu?
  • [00:17:29] <ka6sox-away> mranostay: look up UGT
  • [00:18:10] <mranostay> ka6sox-away: UGT?
  • [00:18:32] <ka6sox-away> let me find it for you :D
  • [00:19:22] <mranostay> heh
  • [00:19:29] <mranostay> this --> http://thinkmoult.com/ugt.html ?
  • [00:20:06] <ka6sox-away> http://www.total-knowledge.com/~ilya/mips/ugt.html
  • [00:20:31] <ka6sox-away> yes, that one
  • [00:26:53] * mranostay sips his tea and some Aspirin
  • [00:27:12] <mranostay> ka6sox-away: so what apps are writing for the FPGA cape?
  • [00:27:32] * ka6sox-away remembers the last comment mranostay said last night...
  • [00:27:44] <ka6sox-away> mranostay, "apps"...
  • [00:27:45] <ka6sox-away> ?
  • [00:28:18] <mranostay> deja vu
  • [00:28:40] <mranostay> ka6sox-away: ok what are you going to load onto the FPGA to make it useful :)
  • [00:28:59] <ka6sox-away> oh, i have a Pong Game I was going to load up in it..
  • [00:29:23] <mranostay> overkill a bit? :)
  • [00:29:31] <ka6sox-away> just a bit
  • [00:29:59] <ka6sox-away> for S/G I was going to load up a AES Decoder...
  • [00:30:29] <ka6sox-away> but that requires me to get the GPMC happy first
  • [00:32:59] <ka6sox-away> if I do it right it should only be 13clock cycles behind.
  • [00:36:03] <ka6sox-away> mranostay, you have something good to use it for?
  • [00:39:32] <mranostay> not really.. probably not thinking hard enough though
  • [00:40:00] <mranostay> started coding the PRU applications for nixie cape
  • [00:40:25] <ka6sox-away> kewl...
  • [00:40:39] <ka6sox-away> what voltage on the anode for that?
  • [00:41:13] <mranostay> it is a VFD tube techically..
  • [00:41:33] <mranostay> so i have it at 36V (rated higher)
  • [00:41:52] <mranostay> 5V for the control grid
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  • [01:43:58] <mph_> afternoon
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  • [04:59:14] <mranostay> hi emeb_mac
  • [04:59:22] <emeb_mac> hi mranostay
  • [04:59:42] <emeb_mac> having a good weekend?
  • [05:00:23] <mranostay> minus the hangover recovery yes :)
  • [05:01:36] <mranostay> emeb_mac: are you going to have any access to the FPGA cape minus the GPMC interface?
  • [05:02:23] <emeb_mac> mranostay: not sure what you just asked.
  • [05:03:06] <mranostay> emeb_mac: how many logic outputs does this FPGA have?
  • [05:04:07] <mranostay> i was thinking it would make sense to hook up a few to the PRU input pins
  • [05:04:11] <ka6sox-away> mranostay, you can use i2c or SPI?
  • [05:04:17] <emeb_mac> Ah - 24 bits from the FPGA are brought out to a 28-pin 0.1" 2-row header
  • [05:04:27] <ka6sox-away> yup
  • [05:04:58] <emeb_mac> but if you don't want to use the GPMC then you can route anything else to the GPMC GPIO pins
  • [05:04:59] <mranostay> ah that works as well
  • [05:05:19] * mranostay kicks cat off keyboard
  • [05:05:53] <emeb_mac> so if the PRU can talk to those signals on P8 connector then you can go wild
  • [05:06:12] <ka6sox-away> yup
  • [05:06:21] <mranostay> yeah it can
  • [05:06:33] <emeb_mac> and you can still do low-bandwidth comm to the FPGA thru SPI0
  • [05:09:10] <emeb_mac> for example - I see that many of the pins on P8 can carry MMC data. So if you wanted to design an SDIO peripheral into the FPGA and hook to it via MMC that would work too.
  • [05:09:55] <emeb_mac> (I've got a full list of signals that are routed to the FPGA on the web page - http://ebrombaugh.studionebula.com/embedded/bcc/index.html)
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  • [06:47:19] <mranostay> oh fun the pru memory example is the old mmap /dev/mem
  • [06:49:57] <ka6sox> yup
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  • [10:43:58] <_av500_> g
  • [10:43:59] <_av500_> m
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  • [19:41:55] <mranostay> morning gentlemen and trolls
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  • [23:35:09] * Cykon (4c5f8022@gateway/web/freenode/ip.76.95.128.34) has joined #beagle
  • [23:35:51] <Cykon> Hmm, so i'm trying to boot up my beagleboard for the first time... got everything configured (hopefully) correctly on my SD card... yet all i'm getting on my screen is an orange beagleboard.org logo
  • [23:35:53] <Cykon> any ideas?
  • [23:38:30] <W1N9Zr0> see what the serial console says
  • [23:44:17] * Russ (~russ@pool-74-100-57-85.lsanca.fios.verizon.net) has joined #beagle
  • [23:47:57] <Cykon> :( I didn't get one, though I suppose it's probably a good idea to at this point
  • [23:52:47] * mythos (~mythos@unaffiliated/mythos) Quit (Read error: Connection reset by peer)
  • [23:55:53] <Cykon> Does anyone here have experience with using Narcissus for the beagleboard?
  • [23:57:17] <thurbad> sure
  • [23:57:44] <Cykon> When booting up a new image from Narcissus on my board for the first time, what can I expect to see?
  • [23:58:07] <Cykon> I understand that it's supposed to take awhile, but I only see a BB logo, though there's some LED activity on my board
  • [23:58:18] <thurbad> depends on which mlo, uboot, and uimage you use
  • [23:59:54] <thurbad> if you have an orange screen with a beagle logo it's probably an old MLO