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  • [00:00:44] * Topic is 'http://beagleboard.org/chat has a guide on how to ask questions and links to the logs | never ask to ask, just ask | be patient | pastebin a boot log | http://ahsoftware.de/Beaglebone_Black_Boot_explained.svg | http://beagleboard.org/latest-images | http://beagleboard.org/Support/bone101 | direct bonescript/node.js questions to #beagle-bonescript | books: http://bit.ly/bbb-books'
  • [00:00:44] * Set by jkridner!~jkridner@pdpc/supporter/active/jkridner on Fri Jan 30 15:50:42 UTC 2015
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  • [00:14:27] <vvu> kpj: Jacobs University Bremen ?
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  • [00:15:24] <kpj> vvu: Yes? :-)
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  • [00:30:08] <GenTooMan> has anyone done hardware interfacing with their BBB (a bit more than using I2C or spi that is)
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  • [00:37:31] <agmlego> Yes.
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  • [01:46:02] <pehjota> kpj: Yeah, that likely signifies that your kernel (Linux) is hung, panicing, or not booting or that your bootloader (MLO/SPL or U-Boot) isn't booting.
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  • [02:35:11] <GenTooMan> <agmlego> sorry stepped out (heh) I was looking at the power sub system on the BBB is 2A for the 5V supply adequate with decoupling caps near the connector? Do I need to consider high speed bus use for using any of the SPI bus etc? The PRU seems to be unuseable for high speed communication so straight to the main processor seems the last route available. I couldn't find more than 2 USB DM / DP connections and they are both
  • [02:35:11] <GenTooMan> routed on the board (IE I can't make an embeded USB hub on the thing either).
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  • [02:36:36] <agmlego> GenTooMan: Maybe if you gave me more details on what you are trying to do, or even just asked a question, I might be able to help.
  • [02:38:04] <agmlego> 2A @ 5V is recommended if you want stable operation of the board, and want to power things off the USB port. If you need no USB power, you can get away with 1.5A.
  • [02:38:05] <GenTooMan> I was planning on connecting a high speed SPI (37mhz) device however I'm concerned about the noise (1.8V bus single ended)
  • [02:38:29] <agmlego> 37MHz is pretty high clock rate for SPI, are you sure the slave device supports that high a clock frequency?
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  • [02:40:33] <GenTooMan> Ok I was looking in terms of general PSU I was thinking of a USB keyboard into the main USB Host connector but I also would like to allow a USB flash drive too so hmmm hub was my next though. And yes it does. I was thinking of slaving it straight to the BBB however noise wise since it's actually a precision analog device I am really puzzled. So I'll have to rethink that.
  • [02:40:40] <zmatt> eh, you can't make 37 MHz, it's either 48 or 24
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  • [02:41:00] <zmatt> since McSPI gets an 48 MHz functional clock
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  • [02:41:27] <agmlego> GenTooMan: "precision analog device"...and yet you are wooried about noise from the SPI bus?
  • [02:41:28] <GenTooMan> thanks zmatt I did read the data sheet but DAMN it's huge.
  • [02:41:42] <zmatt> GenTooMan: still very incomplete though
  • [02:41:52] <agmlego> GenTooMan: I suggest using the manufacturer's exact board layout example for the chip you want to use, and everything will be fine.
  • [02:42:08] <GenTooMan> 8 24bit delta sigma converters?
  • [02:42:24] <agmlego> As for USB...it is *always* recommended to use a powered USB hub to avoid tears and sadness.
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  • [02:42:45] <agmlego> GenTooMan: Again, use the application note or provided board layout diagram in the part's datasheet.
  • [02:42:59] <agmlego> GenTooMan: If the manufacturer of the part neglected to provide those, choose a different part.
  • [02:43:25] <GenTooMan> <agmlego> good advise.
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  • [02:44:36] <GenTooMan> I was thinking I might be able to "use A PRU" however it's not looking so good after looking at what pins are available. :D
  • [02:46:49] <GenTooMan> Looks like I have a bit of layout fun ahead of me.
  • [02:47:32] <GenTooMan> Thanks again it's better to ask crazy questions than guess.
  • [02:47:37] <zmatt> point-to-point transmission lines are not *very* hard to get right, ... now once it becomes a star topology that's when the real pain begins (several TI SoCs have a second chip-select for EMIF, but officially defeatured... maybe there's truly something wrong with it, but I wouldn't be surprised they just don't want a ton of customers with a board they can't get to work)
  • [02:48:29] <zmatt> of course DDR is a bit trickier still than 48 MHz SPI ;)
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  • [02:53:00] <zmatt> GenTooMan: note btw that if you don't need hdmi you can repurpose those pins (e.g. for PRU)
  • [02:54:12] <GenTooMan> <zmatt> but I love pretty pictures! Actually I need the LCD lines to be precise (800x480 7" LCD) I'll have too look to see if I can mess with the mux some to use alt lines.
  • [02:55:47] <GenTooMan> My guess is I'll end up using a low end FPGA and grab the data from the A2D's from that (sigh) nothing is ever simple.
  • [02:55:58] <zmatt> ultimately the am335x is still a pretty small SoC, if you want crazy stuff wait for vayu ;P
  • [02:56:08] <zmatt> hmm, speaking of, is it released yet?
  • [02:56:30] <GenTooMan> You mean the new SoC's for car infotainment?
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  • [02:57:06] <zmatt> the crazy thing of which the "lite" version is the am527x on the beagleboard-x15
  • [02:57:26] <zmatt> (the high-end versions aren't for car infotainment but ADAS btw)
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  • [03:00:16] <GenTooMan> It would be nice if they would put some of those 64bit ARMs with 64bit buses and real big space. I was eyeing the keystone SoC's which are a bit bigger but I am not going to do any BGA layout I have trouble enough with QFN
  • [03:00:36] <zmatt> still weird that a chip with ARM + DSP + IVA-HD + video processing gets branded as a Sitara AM-part... that feels kind of like a death sentence for the DaVinci brand
  • [03:00:42] <zmatt> lol, a bit bigger...
  • [03:01:23] <GenTooMan> 4 arm cores and dsp cores nice huh?
  • [03:02:07] <GenTooMan> Oh yes the 2 1G and built in ethernet switch with 4 100T lines Ld
  • [03:02:12] <zmatt> keystones are afaik intended for things like 4G cellular barestatiosn
  • [03:02:50] <GenTooMan> Yes but they would make a great mini super computer
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  • [03:03:39] <zmatt> (the WCDMA receive and transmit coprocessors, turbo decoders, viterbi decoders, "bit rate coprocessor" supporting "WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A and WiMAX Uplink and Downlink Bit Processing" are also a hint of course)
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  • [03:04:45] <zmatt> there's some crazy PCI card with four KS2s on it (total 16 DSP cores)
  • [03:04:46] <GenTooMan> Great for sattelite com
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  • [03:05:58] <GenTooMan> Or over land short haul point to point (could get 50km with proper noise floor) big issue them becomes earth curvature of course (stupid earth getting in the way)
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  • [03:06:56] <zmatt> but you get relatively little "normal IO" on keystones... like they only added USB (one port) in keystone2, and even the am335x has more GPIO
  • [03:08:23] <zmatt> (and they're... not cheap)
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  • [03:11:07] <zmatt> but vayu is pretty nuts too in a different way... although not all of it available on the am527x, that thing has iirc 10 digital video inputs :P
  • [03:12:44] <zmatt> *am572x
  • [03:16:57] <zmatt> also, if you need another pin available, at least on my BBB (an A5A) the eMMC reset signal isn't actually enabled in the eMMC device, so the pin is ignored
  • [03:17:00] <zmatt> :P
  • [03:18:26] <GenTooMan> I've noticed most of TI's SoC's are a bit too specialized at times.
  • [03:19:19] <zmatt> they're made for one or a few big application domains, and the leftovers become broadmarket parts
  • [03:20:40] <GenTooMan> Seems a repeated pattern of 'over thinking' parts. Atmel has more broad scoped parts and they do better in industrial as a consequence.
  • [03:21:37] * zmatt has no idea how well TI is doing, so has no comment really
  • [03:22:08] <zmatt> intuitively I can understand the strategy of going for hw + sw "solutions"
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  • [03:23:08] <GenTooMan> Their arm line ... for industrial I will politely call "tolerable" but can't be used?
  • [03:23:45] <zmatt> well the am335x *is* specifically targeted at industrial applications
  • [03:24:02] <GenTooMan> The BBB SoC is the BEST of their industrial parts and it's all quirky :D
  • [03:24:33] <zmatt> I haven't met a processor yet that *isn't* quirky
  • [03:24:46] <bwarff__> im glad the am335 thing has a regular m4 instead of the oddball pru, might have more generalised support ?
  • [03:25:54] <zmatt> bwarff__: you mean the am572x ? it has two dual-core cortex-m4 subsystems (four cores total) *and* two PRU subsystems (four cores total)
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  • [03:26:11] <bwarff__> my mistkae
  • [03:26:14] <zmatt> the M4 is no replacement for PRU though
  • [03:26:18] <GenTooMan> A standard ISA is wonderful in terms of support.
  • [03:26:20] <zmatt> (nor vice versa)
  • [03:26:40] <bwarff__> the m4 cant share memory with the main cpu ?
  • [03:27:00] <zmatt> eh, sure they can
  • [03:27:11] <zmatt> local memory is faster to access obviously
  • [03:27:27] <bwarff__> what does the pru have then ?
  • [03:28:08] <zmatt> PRU is essentially a fancy bitbang-engine ... it's used to emulate all sorts of weird bus interfaces
  • [03:28:32] <zmatt> which relies on its extremely simple timing
  • [03:31:02] <zmatt> the IPUs (cortex-m4 subsystems) are an evolution of the "ducati" dual cortex-m3 subsystem which is mainly used to micro-manage video-related peripherals without burdening the main cpu (especially since that management may be relatively simple, but is also hard real-time if you don't want video to stall/glitch)
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  • [03:32:05] <zmatt> of course they can also be used for a variety of other applications
  • [03:32:27] <bwarff__> if they make sure their is spme mbed style fat libs for them so they can be used like regular micros it would make that board quite cool
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  • [03:34:29] <zmatt> except they're not regular micros, and never will be
  • [03:35:16] <bwarff__> in what way ?
  • [03:35:44] <zmatt> they're cores on a honkin' bigass SoC, they communicate with peripherals over a packet-switched network
  • [03:35:45] <bwarff__> my hope would be some io pins and the ability to manage sensors/blah independantly of the main cpu
  • [03:36:31] <zmatt> not to mention I don't think I've ever seen a "dual-core" cortex-m3/m4 ... and that's actually slightly tricky to work with since they have exactly the same memory image (apart from the PPB)
  • [03:36:55] <zmatt> (there is an MMU but it's shared by the two cores, no separate mappings)
  • [03:38:35] <zmatt> but sure you could reserve some peripherals/io for them specifically
  • [03:38:41] <GenTooMan> The hercules IC does the same thing with ARM cores for ultra high reliability
  • [03:38:51] <zmatt> hmmm that's not the same thing
  • [03:38:56] <bwarff__> the new imx6 blah does aswell i think
  • [03:38:59] <zmatt> the IPU cores don't run in lock-step
  • [03:39:01] <zmatt> they're independent
  • [03:39:22] <GenTooMan> hrmm Guess so but the concept is similiar no?
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  • [03:39:44] <zmatt> no
  • [03:40:04] <zmatt> two cores in lock-step behave like one core
  • [03:40:07] <zmatt> but more reliable
  • [03:41:28] <zmatt> also they use cortex-R, not -M
  • [03:42:01] <GenTooMan> -R rotten right? :D
  • [03:42:50] <zmatt> btw, don't forget the am335x has a cortex-m3 also... it's officially just intended for assisting with suspend/resume, but that doesn't mean you can't use it for other purposes... the main limitation is that it only connects to the L4WK which limits the peripherals you can use
  • [03:43:11] <zmatt> (unless you use some ugly hack involving EDMA)
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  • [03:45:20] <GenTooMan> ohhh that sounds like fun ... heh Actually good for turning stuff on and off but IO access of some sort would be handy.
  • [03:45:40] <zmatt> the L4WK is not devoid of peripherals :P
  • [03:47:31] <zmatt> two of the two timers, one gpio bank, one uart, one i2c, and the adc/tsc
  • [03:48:02] <bwarff__> uart and an i2c covers lots of cases.
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  • [03:49:03] <zmatt> and you'll need to avoid writing bloatware, since the cortex-m3 has only 24 KB memory total and no (direct) access to main memory
  • [03:49:42] <GenTooMan> Looks like it's primary purpose is to keep things operating can it force the main processor to reset?
  • [03:50:06] <bwarff__> if it can manage the power to the main processor its perfect for our use cases actually.
  • [03:50:25] <bwarff__> which is a micro doing basic sensor jobs and waking up the big board when things get interesting.
  • [03:50:41] <zmatt> it doesn't keep anything operating, it's in reset until the cortex-a8 loads firmware onto it (I'm not even sure mainline linux does at all), and then spends most of its time in WFI
  • [03:52:01] <zmatt> when the cortex-a8 wants to suspend, it informs the m3 of the relevant wakeup sources, requests PRCM to turn itself off, then enters WFI to acknowledge PRCM's idle-request
  • [03:52:22] <zmatt> if it succesfully enters idle, the M3 gets an IRQ and is now in charge
  • [03:53:24] <zmatt> it can then make sure the relevant wakeup sources are enabled, and turns off the light
  • [03:55:11] <zmatt> I'm not sure it can forcibly reset or powerdown the cortex-a8... it might, but it's not meant to... the cortex-a8 is supposed to cooperate by entering WFI
  • [03:56:53] <zmatt> (also to ensure all pending interconnect transactions are finished, some previous SoCs had problems where the cortex-a8 could be suspended with a transaction still open, leading to desynchronization and lockup requiring chip reset to resolve)
  • [04:00:42] <bwarff__> sounds sane enough
  • [04:01:44] <zmatt> also, with a minor hw patch the cortex-m3 can use JTAG on the SoC and totally 0wn the cortex-a8 ;)
  • [04:04:09] <GenTooMan> that would be good for bugging err debugging
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  • [04:10:47] <zmatt> https://github.com/dutchanddutch/jbang
  • [04:11:53] <zmatt> still contains a minor issue though... I kinda assumed bitbanging this way would be "slow enough", but there are indications this may not be the same so actual delays should be inserted
  • [04:13:04] <zmatt> and it's still missing an OCP barrier necessary to guarantee ordering between control module writes and gpio reads
  • [04:14:05] <zmatt> watchpoints are very useful though, and it's annoying you have to jump though such hoops to allow the cpu to use them
  • [04:18:29] <GenTooMan> I've learned that SW delays never work right. You can use the timers you have for help with delays that are consistent at least.
  • [04:18:48] <zmatt> eh, why wouldn't usleep work right?
  • [04:18:55] <zmatt> (note that there's no harm in delaying too much)
  • [04:19:11] <zmatt> (in this case)
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  • [04:22:04] <GenTooMan> Well I had a 40 usec delay on a radio loop SW wasn't consistent enough (stupid radio hardware) so I had to use a timer to wake the processor up after it counted correctly. Didn't have a magic usleep so HW was put too good use. Delays cost you on RF com (I hate radio com).
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  • [04:23:10] <GenTooMan> Anyhow I'lll see if I can dig up my old BBB project and look at what I did to make sure power isn't messed up.
  • [04:23:21] <GenTooMan> night all
  • [04:23:22] <zmatt> ok, but that's a very different situation.. jtag doesn't require any consistent timing
  • [04:23:34] <GenTooMan> Lucky you huh? :D
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  • [04:24:33] <zmatt> I should probably get some sleep too
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  • [06:05:46] <kiran4399__> Anyone mentoring for PRUduino ? High-level language support with PRU ?
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  • [06:18:56] <CPUMAN_> When controlling the LEDS on the BBB, I am using the /sys/class/led/beaglebone:green:usr0 as instructed. Is the beaglebone:green:usr0 actually a device driver with source code that I can use to build my own version?
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  • [06:19:32] <av500> its a kernel driver
  • [06:19:41] <av500> exposed via the sys filesystem
  • [06:20:00] <av500> yes, source is available
  • [06:20:12] <av500> but for GPIOs and LEDs you dont need to write a new driver
  • [06:22:36] <CPUMAN_> OK. The reason that I ask is I am needing to port a device driver from Gumstix to BBB and wanted to tickle the LEDS to make sure my driver is working. Also wanted to use the beaglebone:green driver as a starting point. Sounds like I may be on the correct path.
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  • [06:23:16] <av500> what kind of driver?
  • [06:23:20] <tbr> why leds if you can just print to kernel console (UART)?
  • [06:23:33] <av500> UART is so 90's
  • [06:23:47] <tbr> yeah, not even nation state actors need UARTs
  • [06:23:55] <CPUMAN_> It is a driver to an FPGA
  • [06:24:04] <av500> ah
  • [06:24:12] <CPUMAN_> SO I will be using mapped memory
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  • [06:25:29] <CPUMAN_> Thanks for your help. Today is first day getting BBB up and running. Sure is a nice platform.
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  • [06:47:40] <ds2> have fun with GPMC
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  • [12:44:52] <CleitonBueno> Hi
  • [12:45:12] <CleitonBueno> I customize Linux embedded to Beaglebone Black with Yocto Project... Perfect!
  • [12:45:52] <CleitonBueno> My problem is with net-snmp... install OK.. but to start...
  • [12:46:24] <CleitonBueno> pcilib: Cannot open /proc/bus/pci
  • [12:46:32] <CleitonBueno> snmpd[15460]: pcilib: Cannot find any working access method.
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  • [12:47:41] <CleitonBueno> Command lspci same problem
  • [12:47:44] <Vibouk> Hi, I just switched to Debian on my BBB and i'm looking for the apporpriate toolchain for the cross-compilation from windows
  • [12:48:09] <Vibouk> And I don't find any
  • [12:49:35] <tbr> CleitonBueno: the device doesn't have pci, that's why
  • [12:50:14] <tbr> Vibouk: I'd recommend a debian wheezy VM. Should be much easier to cross-compile.
  • [12:51:12] <CleitonBueno> OK, I know.. but in version net-snmp 5.7.2.1 fix this BUG PCI... same problem continue
  • [12:51:18] <Vibouk> ho really? I used to cross-compile for Angstrom successfully and quite easilly
  • [12:51:39] <CleitonBueno> In Yocto Project the fix in ifmib.patch in the recipe net-snmp
  • [12:51:41] <tbr> Vibouk: ok, then you might go down that same route
  • [12:51:46] <Vibouk> If I don't have the choice, I will install debian on my pc
  • [12:55:05] <CleitonBueno> <Vibouk> Suggestion?
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  • [12:55:39] <Vibouk> yeah, I will try to find the good toolchain
  • [12:56:13] <Vibouk> CleitonBueno: What's your problem?
  • [12:57:08] <Vibouk> tbr : I will try the Linaro-gcc Toolchain
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  • [12:57:26] <CleitonBueno> Up net-snmp (snmpd service) and not possible
  • [12:57:37] <CleitonBueno> Error Cannot open /proc/bus/pci
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  • [12:58:01] <CleitonBueno> OK, I know.. but in version net-snmp 5.7.2.1 fix this BUG PCI... same problem continue
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  • [12:59:13] <Vibouk> umm msorry I don't have access to my BBB at the moment so i'm not of any help
  • [13:02:10] <CleitonBueno> Strange .. in linux default of BEAGLEBONE lspci command nor is there and the /proc/bus/pci does not exist and the error
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  • [15:23:54] <mistawright> hi guys I have been trying to get my beaglebone black to take commands from my dualshock3 controller. I have gotten the controller paired and can run some test programs to see input but i cant seem to get things mapped right. I came across some c++ defines on the ros website but those dont seem to work properly either
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  • [16:07:21] <abch> hi everyone ! how can i take a single bit input using a push button ?
  • [16:08:37] <blaine> abch: look up gpio
  • [16:09:20] <blaine> abch: http://www.linux.com/learn/tutorials/765810-beaglebone-black-how-to-get-interrupts-through-linux-gpio
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  • [16:13:45] <Mikaela> OK, so I finally got myself to the beagle with the exact same procedure that Jolla recovery mode used and what was my issue with it
  • [16:13:45] <Mikaela> 1. ifconfig -a, 2. ifconfig eth1 192.168.7.1 3. go to http://192.168.7.2/ using webbrowser
  • [16:14:01] <Mikaela> this is so important, why I never learned steps 1 & 2 before during these years
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  • [16:34:16] <abch> blaine: i followed this tutorial http://elinux.org/images/b/b7/Beaglebone_-_Hands_on_Tutorial.pdf
  • [16:36:28] <blaine> so you should be good to go
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  • [16:38:59] <abch> blaine: but when i keep pressing the button i need only one output ... how can i go about doing that ?
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  • [16:40:33] <_av500_> what do you mean?
  • [16:40:57] <blaine> abch: the link i sent earlier exactly describes a push button over gpio -- you should follow that and report back
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  • [16:42:53] <abch> blaine: okay
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  • [19:43:35] <Catslab> rcn-ee: on osx there's a trouble when packing kernel modules, missing some files like modules.alias, modules.dep and so on
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  • [20:12:22] <rcn-ee> Catslab, wonder what generates those..
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  • [20:23:05] <Catslab> I'll find :)
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  • [20:23:39] <Catslab> I'm sure this has something to do with the xargs and so on
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  • [20:35:51] <rcn-ee> Catslab, with a lot of these fixes, you should push mainline.. someone might want to boot linux on a mac osx userspace.. ;)
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  • [21:46:27] <_Pink> hey all. quick question. if I have a prebuild qnx IFS that I am trying to boot using qemu (beaglexm), how would I get it in to, or extract from it, a binary in the zImage format?
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  • [23:37:49] <tholm> I got a bbb rev a6 and another rev c. I'm running my FS on a RAMDISK and this the question: Why u boot load the image on rev c faster than rev a6 ?
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  • [23:39:02] <tholm> eMMC on Beaglebone Black rev is faster than rev a6a?
  • [23:39:10] <tholm> rev c*
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