Beagle Board -

Beaglebone-Spartan6 Cape

Entry name Beaglebone-Spartan6 Cape
Description A Xilinx Spartan-6 fpga (XC6LX25) equipped cape connected to the beaglebone over the I2C, SPI, and GPMC lines. The fpga has 24k logic cells and 40 IO lines bought out to play with. For use as a data buffer a 32MB SDRAM is connected to the fpga. The board supplies 5V to the beaglebone, and allows the user to select the voltage on the 40 user accessible fpga IO's. The intention of the board is to be a platform to experiment with fpga co-processors, hardware/software co-design, and the concept of peripherals on demand. The beaglebone will be able to directly configure the fpga at any time. My goal is to get the board and it's software to a point where a software frame work is able to provide both the hardware modules in HDL and the drivers for hardware module use. The user will be able to instantiate the hardware they need, and have the drivers to interface with it. The board coupled with the beaglebone would be an excellent platform for Software Defined Radio, and high speed signal acquisition. I already have thoughts about connecting high speed ADCs over LVDS to the fpga. For speed, the GPMC lines are length matched to within 8mm of each other, including accounting to length differences in the Beaglebone A3 (the only one I have, but can easily change the lengths if needed). Before final release, the fpga IO differential pairs will be matched to ensure the best possible performance. I started this project back in June when looking for an fpga add on board for the beaglebone, similar to what exists for the original beagleboard, the pandaboard, and the Armadeus Project. Finding a few that had no updates for a long time, or weren't available to purchase, I began my own design. 6 months later here is my board. I want to share it with the beagleboard community, and this contest is a great way to do so. All my design files are on git-hub, and I welcome any and all feedback. Video show casing my design to come soon!
Project URL
Submitter Michael Magyar

Projected created on: Mon Dec 17 2012 06:57:44 GMT-0000 (UTC)
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Last updated on: Wed Jan 02 2013 19:05:09 GMT-0000 (UTC)